The present invention relates to semiconductor device fabrication, and more particularly to a method of fabricating an implanted back-gated fully depleted complementary metal oxide semiconductor (CMOS) device in which the implanted back-gate controls the threshold voltage of the front-gate device. The present invention also relates to an implanted back-gated fully depleted CMOS device comprising, among other elements, an implanted back-gate that controls the threshold voltage of the device.
Simultaneous reduction of supply and threshold voltages for low-power silicon-on-insulator (SOI) CMOS design without suffering performance losses will eventually reach the limit of diminishing returns as static power dissipation becomes a significant portion of the total power equation. In order to meet the opposing requirements of high-performance during circuit/system active periods, and low-power, during circuit/system idle periods, a dynamic threshold voltage control scheme is needed.
For SOI metal oxide field effect transistors (MOSFETs), there are two modes of operation: 1) fully depleted, and 2) partially depleted channel region. In conventional strongly fully depleted SOI devices, the silicon film thickness is usually less than or equal to half the depletion width of the bulk device. The surface potentials at the front and back interfaces are strongly coupled to each other and capacitively coupled to the front-gate and substrate through the front-gate dielectric and the buried oxide, respectively. Therefore, the potential throughout the silicon film, and hence the charge, is determined by the bias conditions on both the front-gate and the substrate. By replacing the substrate with a back-gate, the device becomes a dual-gated device.
The fully depleted design is unique to SOI because the front-gate and the back-gate both have control of the charge in the silicon film. In the strongly partially depleted device, the back-gate or the substrate has no influence on the front surface potential. In the middle regime, the device is nominally partially depleted and can become fully depleted by applying bias, thus, coupling of the front and back surface potentials still occurs.
To date, no adequate dynamic threshold voltage control schemes are present in conventional SOI MOSFET devices; therefore, as these devices are continually being scaled down to smaller sizes, the devices will become extremely leaky when operating under low-power conditions, i.e., when the devices are idle.
In view of the state of the art mentioned above, there is a continued need for providing a SOI MOSFET device that includes a dynamic threshold voltage control scheme that works under circuit/system active periods, as well as circuit/system idle periods.
The present invention is directed to a SOI MOSFET device that includes a dynamic threshold voltage control scheme, which is suitable for both high-performance, i.e., circuit/system active periods, and low-power, i.e., circuit/system idle periods, applications. Specifically, the present invention provides a SOI MOSFET device comprising an implanted back-gate region which controls the threshold voltage of the front-gate. NMOS and PMOS back-gates are also present which are switched independently of each other and the back-gate. The front-gate threshold voltage may be controlled over the range between strong accumulation and strong inversion of the back interface.
In the device aspect of the present invention, a SOI MOSFET device is provided that comprises:
a silicon-on-insulator substrate comprising a first Si-containing layer located atop a buried oxide layer, said Si-containing layer including an implanted back-gate region present therein;
a second Si-containing layer located atop said first Si-containing layer, wherein a portion of the second Si-containing layer serves as a body region for a MOSFET; and
a polysilicon gate located atop said body region.
The present invention also provides a method of fabricating the above-mentioned SOI MOSFET device. The inventive method utilizes processing steps that are compatible with conventional CMOS processes. Specifically, the method of the present invention comprises the steps of:
providing an initial SOI wafer which includes at least a first Si-containing layer located atop a buried oxide region, said first Si-containing layer having an implanted back-gate region located therein;
providing a second SOI wafer having at least an oxide layer formed atop a second Si-containing layer;
bonding said SOI wafers together to provide a bonded structure in which the oxide layer of the second wafer; is bonded to the first Si-containing layer of the initial SOI wafer;
exposing the second Si-containing layer of the bonded structure;
converting a portion of said exposed second Si-containing layer into a body region; and
forming a gate dielectric and a polysilicon gate atop said body region.
Additional BEOL processing steps, as described herein below, can also be performed following polysilicon gate formation.